1. The Field of the Invention
The present invention relates generally to analog circuits. More specifically, the present invention relates to low-voltage differential signal transmitters that have high signal integrity.
2. Background and Relevant Art
Electronic circuitry provides complex functionality that is proving ever more useful. Electronic circuitry pervades our modern lives in areas such as communication, entertainment, travel, productivity, and the like. One useful circuit is the differential signal transmitter.
Differential signaling offers several advantages over single-ended signaling. One is a significant reduction in Electro Magnetic Interference (EMI). Magnetic fields induced by one differential signal path tend to cancel out with magnetic fields induced by the other differential signal path. Differential signaling is also more resistant to negative effects of common mode noise. Differential signaling has been employed for some time.
More recently, Low Voltage Differential Signaling (LVDS) standards have been developed to employ differential signaling at higher throughputs and lower power than more traditional differential signaling technologies. Nevertheless, even conventional modern low voltage differential signaling has some drawbacks as will now be described with respect to FIG. 10.
FIG. 10 illustrates a conventional low voltage differential signaling output driver circuit 1000 in accordance with the prior art. Two voltage rails are provided, a high voltage rail 1001 and a low voltage rail 1002. As illustrated, the high voltage rail may be a voltage source at Vdd, which in low voltage applications may be, for example, 3.3 volts or 2.5 volts. The low voltage rail 1002 may be ground.
P-type Field Effect Transistor (PFET) 1013 and N-type Field Effect Transistor (NFET) 1017 serve as a current source and sink, respectively. The current source PFET 1013 is biased by voltage PB applied at bias terminal 1003, while the current sink NFET 1017 is biased by voltage NB applied at bias terminal 1004. The output differential voltage between output terminals 1008 (PADMN) and 1007 (PADMP) is a sum of two voltage drops: one across resistor 1009 and one across resistor 1010. By switching the voltage at switching terminals 1005 (RISE) and 1006 (FALL) in the opposite direction, current flowing through the two resistors 1009 and 1010 is likewise switched to the opposite direction. This changes the polarity of the differential voltage between output terminals 1007 and 1008.
For example, when the input voltage on switching terminal 1005 is high (and the input voltage on switching terminal 1006 is correspondingly low), PFET 1011 and NFET 1016 are on. This allows a current from the high voltage source 1001 to flow through current source PFET 1013, switching PFET 1011, resistors 1009 and 1010, switching NFET 1016, current sink NFET 1017 and into the low voltage source 1002. This current creates a positive differential across output nodes 1007 and 1008. Conversely, when the input voltage on switching terminal 1005 is low (and the input voltage on switching terminal 1006 is correspondingly high), PFET 1012 and NFET 1015 are on. This allows a current from the high voltage source 1001 to flow through current source PFET 1013, switching PFET 1012, resistors 1010 and 1009, switching NFET 1015, current sink NFET 1017 and into the low voltage source 1002. This current creates a negative differential across output nodes 1007 and 1008.
Due to Miller capacitive coupling between nodes 1005 and 1008 and between nodes 1006 and 1007, a significant overshoot and undershoot may be observed on node 1007 and 1008 when nodes 1005 and 1006 are switching. This overshoot and undershoot degrades signal integrity.
Specifically, the differential voltage between output terminals 1007 and 1008 ranges in magnitude from around 0.25V to around 0.45V according to the LVDS specification. Voltage swings on the input terminals 1005 and 1006 are from ground to Vdd and have a magnitude of the entire voltage supply (e.g., ground to 3.3V or ground to 2.5V depending on the supply voltage). Compared with a small differential across output terminals 1007 and 1008, the voltage swing on the input terminals 1005 and 1006 is significantly about one order of magnitude greater. Even a small Miller coupling ratio in the switching transistors would pass a significant amount of voltage from the input terminals 1005 and 1006 to the output terminals 1007 and 1008. Furthermore, in order to obtain the required throughput performance, the slew rates at input terminals 1005 and 1006 are not controlled and are normally designed to be as fast as possible. This further degrades signal integrity.
Also, the conventional LVDS driver does not have skew control between the two pre-driving signals asserted on the input terminals 1005 and 1006. Ideally there should be zero skew between those two voltages of opposite polarity. Uncontrolled skew between them would significantly distort the output voltage across the output terminals 1007 and 1008, particularly in varying the common mode voltage on common mode voltage terminal 1019.
Accordingly, what would be advantageous is an LVDS driver that has better signal integrity and controlled skew on its input terminals.